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Journal Articles Journal of Systems Architecture Year : 2019

Ker-ONE A new hypervisor managing FPGA reconfigurable accelerators


In the last decade, research on CPU-FPGA hybrid architectures has become a hot topic. One of the main challenges in this domain is to efficiently and safely manage Dynamic Partial Reconfiguration (DPR) resources. This paper focuses on the management of reconfiguration by a custom hypervisor named Ker-ONE, on an ARM-FPGA platform. Using a virtualization approach, virtual machines (VM) may access resources independently, being unaware of the existence of other VMs. Our custom hypervisor guarantees the independence and isolation of VM domains. The purpose of our work is to provide an abstract and transparent interface for virtual machines to access reconfigurable resources, while meeting real-time constraints. This means that software engineers do not need to focus on implementation details. In this paper, we present a complete architecture in which hardware accelerators are seen as virtual devices which are universally mapped in each VM space as ordinary peripherals. The hypervisor automatically detects VMs’ requests for DPR resources and handles them dynamically according to a preemptive allocation mechanism. We also evaluate the efficiency of our framework by measuring the critical overhead during DPR management and allocations. The results demonstrate that our mechanisms are implemented with low overhead compared to other approaches and that they are compatible with real-time scheduling. © 2019
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hal-02161023 , version 1 (14-11-2019)



T. Xia, Y. Tian, Jean-Christophe Prévotet, F. Nouvel. Ker-ONE A new hypervisor managing FPGA reconfigurable accelerators. Journal of Systems Architecture, 2019, 98, pp.453-467. ⟨10.1016/j.sysarc.2019.05.003⟩. ⟨hal-02161023⟩
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