Dual-gate and gate-ail-around polycrystalline silicon nanowires field effect transistors Simulation and characterization - Université de Rennes Access content directly
Conference Papers Year : 2018

Dual-gate and gate-ail-around polycrystalline silicon nanowires field effect transistors Simulation and characterization

Abstract

Polycrystalline silicon nanowires (poly-SiNWs) are synthesized using side wall spacer top-down method and classical photolithography techniques. This low-temperature (≤ 600°C) fabrication process is a low cost and fully compatible with planar complementary metal oxide semiconductor (CMOS) silicon technology. Independent biasing of each gate allows a possible threshold voltage control of the bottom gate transistors (BOT) and top gate transistors (TGT). Moreover, a new gate architecture passing from 2D to 3D, surrounding-gate transistors, called Gate-All-Around (GAA) where the gate circles the nanowire channel, allows a better electrostatic gate control. Numerical modeling of dual-gate structure and simulations are performed to estimate electrons and holes concentrations in the nanowire used as active layer versus applied gate voltages. Electrical performances of top and bottom-gate transistors are analyzed highlighting oxide-semiconducting nanowire interfaces difference in top and bottom gate configurations. Finally, GAA transistors characterization show that top channel conduction dominates when bias is applied on the surrounding gate. © 2018 Electrochemical Society Inc.All rights reserved.
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Dates and versions

hal-02042765 , version 1 (20-02-2019)

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Anne-Claire Salaün, Brice Le Borgne, Laurent Pichon. Dual-gate and gate-ail-around polycrystalline silicon nanowires field effect transistors Simulation and characterization. Symposium on Thin Film Transistor Technologies 14, TFTT 2018 - AiMES 2018, ECS and SMEQ Joint International Meeting, Sep 2018, Cancun, Mexico. pp.79-88, ⟨10.1149/08611.0079ecst⟩. ⟨hal-02042765⟩
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