Julia meets the FPGA : Higher-level synthesis methodology forheterogeneous hardware and software architectures
Résumé
Julia has achieved strong result in heterogeneous compilation such as GPU or IPU. But little work has been carried out for Field Programmable Gate Array (FPGA). Although Julia language with its type system, readability and libraries is an excellent fit for High-Level Synthesis (HLS). The idea is to used Julia IR as a MLIR frontend, develop a new toolchain which can generate representation usable by MLIR HLS tools such as ScaleHLS.
Domaines
Architectures Matérielles [cs.AR]Origine | Fichiers produits par l'(les) auteur(s) |
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