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Communication Dans Un Congrès Année : 2000

Fast Power Estimation at the architectural Level

Résumé

With the emergence of embedded processing systems, the power dissipation of very large scale integrated circuits is becoming a critical concern. Therefore power requirements are driving a new breed of computer-aided design tools. This paper addresses the problem of modeling power dissipation at a high level of abstraction. A modeling approach is presented that captures the dependence of the circuit modules power dissipation on theirs activities. We also introduce our RT level estimation tool, PowerCheck,partoftheBSS framework Breizh Synthesis System, http://archi.enssat.fr. PowerCheck takes place after the RTsynthesis, then it by the architecture and its use. The major interest of our approachisthatwe takeinto account the signal properties in our power dissipation estimates of complete architecture.

Domaines

Electronique
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Dates et versions

hal-00986449 , version 1 (02-05-2014)

Identifiants

  • HAL Id : hal-00986449 , version 1

Citer

Matthieu Denoual, David Saillé, Jean Gabriel Cousin, Olivier Sentieys. Fast Power Estimation at the architectural Level. Design of Circuits and Integrated Systems (DCIS), 2000, France. pp 1-9. ⟨hal-00986449⟩
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