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Communication Dans Un Congrès Année : 2012

Hardware Acceleration of SVM-Based Traffic Classification on FPGA

Résumé

Understanding the composition of the Internet traffic has many applications nowadays, mainly tracking bandwidth consuming applications, QoS-based traffic engineering and lawful interception of illegal traffic. Although many classification methods such as Support Vector Machines (SVM) have demonstrated their accuracy, not enough attention has been paid to the practical implementation of lightweight classifiers. In this paper, we consider the design of a real-time SVM classifier at many Gbps to allow online detection of categories of applications. Our solution is based on the design of a hardware accelerated SVM classifier on a FPGA board.
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Dates et versions

hal-00797503 , version 1 (06-03-2013)

Identifiants

  • HAL Id : hal-00797503 , version 1

Citer

Tristan Groleat, Matthieu Arzel, Sandrine Vaton. Hardware Acceleration of SVM-Based Traffic Classification on FPGA. IWCMC TRAC: International Wireless Communications and Mobile Computing Conference, International Workshop on TRaffic Analysis and Classification, Aug 2012, Limassol, Cyprus. ⟨hal-00797503⟩
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