Real-time SER measurements of CMOS bulk 40 nm and 65 nm SRAMS combined with neutron spectrometry at the JET Tokamak during its final D-T plasma operation
Résumé
We performed soft error rate (SER) characterization of 40 nm and 65 nm bulk CMOS SRAMs combined with neutron spectrometry in the deuterium-tritium fueled JET tokamak during its final D-T plasma operation (Sept-Oct 2023) producing a series of several dozens of power pulses. Our experimental results demonstrate the impact of machine operation on the electronics reliability, emulating realistic conditions for circuits exposed to the partially radiation-shielded environment of future fusion reactors. Typical bit flip rates of 493 h -1 Gbit -1 for 65 nm SRAMs and of 2342 h -1 Gbit -1 for 40 nm SRAMs were measured for a residual machine induced neutron flux of ~3.15 x 10 5 cm -2 s -1 below the reinforced concrete slab (thickness of 1,045 mm) supporting the tokamak chamber. To complete this characterization work, a general methodology for the SER prediction in such a mixed-field D-T neutron radiation environment composed of both thermal and fast neutrons (up to 14 MeV) is presented and validated from this ensemble of experimental data for the two SRAM technologies. Finally, the interest of this approach for future tokamaks and high energy physics accelerators is discussed.
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